Supported boards

Two device families are described well enough to build for, and nine boards have been tried. Status here means what someone observed on hardware, not what ought to work.

Follow a board name for its full detail - device resources and how the eight examples fit - or take the whole matrix as boards.json and boards.csv.

Board matrix

Verified means a named person loaded a bitstream from this version or the previous one and watched the design run.
Board	Device	LUT4	Status	Verified	Notes
Pebble-25	T4-25K	24 576	full	0.7.2	Reference board. All eight examples build and run; every release is tested here before tagging.
Pebble-12	T4-12K	12 288	full	0.7.2	Same family, smaller part. The `vga_bars` example fits with 71% occupancy and routes in 21 s.
Fenwick A2	T4-25K	24 576	full	0.7.1	Needs `--config-mode spi-x1`; the default four-bit mode is wired differently on this board and configuration simply fails.
openbench-t4	T4-25K	24 576	full	0.7.2	Community design with published schematics, which is why its pin map in `boards/` is trustworthy.
Marl-45	T4-45K	45 056	partial	0.7.0	Builds and runs, but block RAM cascades are not supported, so no single memory above 4 kbit. Routing a half-full part takes minutes.
Crofter Lite	M1-8K	7 680	partial	0.7.1	No PLL on the part and DDR input registers are unimplemented, so anything above the 25 MHz oscillator is out of reach.
Thistle Edge	T4-12K	12 288	partial	0.6.0	Only the internal oscillator is mapped; the external clock pin is on a bank the device file describes incorrectly. Known bug, not yet fixed.
Dunlin M1	M1-8K	7 680	none	-	Bitstreams build correctly but cannot be loaded: the board's configuration bridge uses an undocumented protocol and nobody has reverse-engineered it.
Harrow X	GX-2	-	none	-	Third device family entirely. No device file exists and writing one is a months-long measurement job, so this is not planned.

What the three statuses mean

full: All eight bundled examples compile, route, pack and run on the board. A named person confirmed this on the current or previous release. Pin map and configuration mode are in the tree.
partial: The board works for designs that avoid a specific missing feature. The missing feature is named in the table, not left as "some limitations apply".
none: Do not spend an evening on it. The reason is given so you can judge whether it is worth fixing.

Device families

PLL counts are what the silicon has, not what the toolchain can use - see the note below.
Part	LUT4	FF	BRAM ×4 kbit	PLL	IO	Bitstream
T4-12K	12 288	12 288	32	1	96	72 704 B
T4-25K	24 576	24 576	64	2	128	141 312 B
T4-45K	45 056	45 056	108	2	192	258 048 B
M1-8K	7 680	7 680	16	0	64	46 080 B

Hard blocks are mostly off limits. Block RAM is inferred only for a single-port synchronous array whose depth is a multiple of 512 and whose width is 1, 2, 4, 8 or 16 bits; anything else becomes flip-flops, silently and expensively. PLLs are never inferred - instantiate HX_PLL by hand with the divider values you worked out yourself, because the tool will not compute them for you. There is no DSP or multiplier primitive at all; a * operator builds an array multiplier out of LUTs and eats the device.

Pin maps

Each supported board has a file in boards/ listing its physical pins, the configuration mode and the on-board clock frequency. A pin map is a plain list, so adapting one for a revision of the same board usually means editing two or three lines:

# boards/pebble-25.board
device      T4-25K
config_mode spi-x4
osc         12.0MHz  pin A7
led         0  pin B3
led         1  pin B4
button      0  pin C9
pmod_a      0..7  pins D1 D2 D3 D4 E1 E2 E3 E4

Those names are what set_io in your constraints file refers to. Using a raw pin designator works too, and is the only option on a board without a map.

Getting a board added

Three things make a board report usable, and they take about an hour to produce:

Which of the eight bundled examples built, and which of those actually ran on the hardware.
The exact hxpack invocation that produced a loadable bitstream, including the configuration mode, plus what the board's own loader printed.
A pin map in the format above, or a link to the board's published schematic so one can be written.

Three of the four full-support boards got there this way. Send reports to hexforge@hexforge.cloud; a board that only ever got a "works for me" message stays off the table, because that sentence has never once been enough.

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supported boards · matrix reviewed 2026-10-03 · see also: limitations