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HexForge Manual
for version 0.7.2, updated 3 October 2026
Nils Haraldsen
This manual documents HexForge 0.7.2. Copyright 2024–2026 the HexForge authors. Verbatim copying and redistribution of this document are permitted under the same two-clause BSD terms as the software; there is no separate documentation licence and no invariant sections.
HexForge
HexForge is four command-line programs that take a restricted dialect of Verilog and turn it into a configuration bitstream for a handful of inexpensive FPGA boards. The source is about 48 000 lines of C++20, it builds in three and a half minutes, and it never opens a socket. This page is the top of the manual; everything else hangs off the node listing below.
Short contents
Detailed node listing
The four programs, in one screen
- hxc
- Reads
.v, writes a flattened gate-and-register netlist.hxn. This is where the language subset is enforced; everything after it is graph work on a netlist that is already legal. - hxsyn
- Reads
.hxn, writes a placed-and-routed design.hxr. Single-threaded on purpose - the placer is deterministic and a second run of the same input gives byte-identical output. - hxta
- Reads
.hxr, prints a timing report and nothing else. It writes no file; pipe it or redirect it if you want to keep it. - hxpack
- Reads
.hxr, writes a.bit. There is deliberately no fifth program to load that bitstream; every board ships a loader that already works.
No binaries are distributed. There is no installer, no package in any distribution's repository, and no container image. You fetch a source tarball from the release directory, check its hash, and build it. The decision not to ship binaries is not laziness; one person cannot test binaries across the matrix of libc versions that would then file bugs.