hexforge / changelog

Changelog

Nine releases. Until 1.0 the middle number may break file formats and flag names, and twice it has; both occasions are marked. Bitstream output has been stable since 0.4.0.

0.7.2 - 2026-10-03

• Router: iteration cap lowered from 60 to 40. Runs that needed more than 40 had never once succeeded, so the extra twenty iterations only delayed the bad news by minutes.
• Pin tables for M1-8K corrected on two banks; Crofter Lite now maps its button row the way the schematic says.
• Fixed a crash in hxc on a generate for whose bounds come from a parameter overridden at instantiation. Reported with a four-line reproducer, which is the ideal bug report.
• Fixed a crash in hxpack when the routed design contains zero flip-flops, as a purely combinational test case did.
• Warning W214 now names the array that failed block RAM inference instead of only its module.
• Examples rebuilt and HASHES regenerated. Verified on Pebble-25, Pebble-12 and openbench-t4.

0.7.1 - 2026-09-07

• Added --config-mode to hxpack with spi-x1 and spi-x4, which is what brought Fenwick A2 to full support. Contributed with a board report and a pin map.
• New warning W204 for an unconstrained clock-domain crossing. Previously such paths were excluded from analysis in silence, which made a two-clock design look better than it was.
• hxta --json output gained the per-path hop counts that the text report already showed.
• Three documentation errors in the constraints syntax corrected after someone followed them literally and got an error.

0.7.0 - 2026-08-22

• Netlist v4 carries explicit clock declarations, which the analyser previously had to infer. That inference was wrong on designs with a clock passed through a module port.
• --chip renamed to --device everywhere. The old spelling errors out naming the new one.
• hxsyn --timing removed; run hxta on the routed design instead. Folding the analyser into synthesis had made it impossible to re-check a design without re-routing it.
• Defect #212 introduced here: the Thistle Edge external clock pin is in the wrong IO bank in the device file.
• Test suite grew to 221 tests.

0.6.0 - 2026-05-14

• Mica M1 family added, starting with M1-8K. Its delay table was measured on a Crofter Lite over a weekend, and its accuracy is the worse of the two families.
• Determinism check added to the release process: all examples built twice on two machines and compared by hash. It immediately found that placement depended on hash-map iteration order, which was fixed in the same release.
• --seed exposed on hxsyn. It existed before as a compile-time constant.
• Defect #198 introduced: the packer still does not understand clock regions, and a two-clock design straddling a boundary gets packed illegally.

0.5.0 - 2026-02-09

• New packer: greedy with one refinement pass, replacing a first-fit version that wasted roughly 18% of a device. Typical designs got between 12 and 20% smaller.
• Block RAM inference for the single-port shape described in the limitations. Before this, every array became flip-flops.
• Defect #164 introduced: dense packing above 94% occupancy fails on M1-8K.
• Carry chain inference for addition and subtraction. Adders stopped being the critical path on every design.

0.4.0 - 2025-10-30

• hxta appeared, with the three corners and the delay tables fitted from ring oscillator measurements. Defect #141 dates from here: the fit extrapolates badly above six routing hops.
• Device frame format frozen. Nothing since has changed the bitstream layout, which is why a 0.4.0 bitstream still loads today.
• T4-45K added, together with the understanding that the router is too slow for a part that size.
• First contributions from outside: two pin maps and a build fix for Clang 15.

0.3.0 - 2025-06-18

• Router replaced with the negotiated-congestion scheme still in use. The previous maze router failed on anything above about 400 LUTs.
• Constraints file introduced with set_io and create_clock; pin assignment had until then been a command-line argument per pin, which was as bad as it sounds.
• vga_bars added as an example, and it was the first design to need a PLL instantiated by hand.

0.2.0 - 2024-11-12

• Parameters, localparam and generate blocks, which is the point at which the subset became usable for real designs rather than demonstrations.
• T4-25K added.
• casex rejected with error E156 after a contributor's design synthesised to something that did not match their simulation. The two-state compiler could not represent what they meant, and failing loudly was the only honest option.

0.1.0 - 2024-05-20

• First public release after about eight months of evenings. One device, T4-12K; one board, Pebble-12; one example, blink.
• Front end accepted modules, wires, registers, continuous assignment and a single clocked block. No parameters, no generate, no memories.
• The maze router could place and route 60 LUT4s. That was enough to blink an LED, and that was the whole goal.