{
 "version": "0.7.2",
 "updated": "2026-10-03",
 "devices": [
  {
   "part": "T4-12K",
   "family": "Tessera T4",
   "lut4": 12288,
   "ff": 12288,
   "bram": 32,
   "pll": 1,
   "io": 96,
   "bitstream_bytes": 72704
  },
  {
   "part": "T4-25K",
   "family": "Tessera T4",
   "lut4": 24576,
   "ff": 24576,
   "bram": 64,
   "pll": 2,
   "io": 128,
   "bitstream_bytes": 141312
  },
  {
   "part": "T4-45K",
   "family": "Tessera T4",
   "lut4": 45056,
   "ff": 45056,
   "bram": 108,
   "pll": 2,
   "io": 192,
   "bitstream_bytes": 258048
  },
  {
   "part": "M1-8K",
   "family": "Mica M1",
   "lut4": 7680,
   "ff": 7680,
   "bram": 16,
   "pll": 0,
   "io": 64,
   "bitstream_bytes": 46080
  }
 ],
 "boards": [
  {
   "id": "pebble-25",
   "name": "Pebble-25",
   "device": "T4-25K",
   "status": "full",
   "verified": "0.7.2",
   "config_mode": "spi-x4",
   "clock_mhz": 12,
   "notes": "Reference board. All eight examples build and run; every release is tested here before it is tagged."
  },
  {
   "id": "pebble-12",
   "name": "Pebble-12",
   "device": "T4-12K",
   "status": "full",
   "verified": "0.7.2",
   "config_mode": "spi-x4",
   "clock_mhz": 12,
   "notes": "Same family, smaller part. vga_bars fits at 71% occupancy and routes in 21 s."
  },
  {
   "id": "fenwick-a2",
   "name": "Fenwick A2",
   "device": "T4-25K",
   "status": "full",
   "verified": "0.7.1",
   "config_mode": "spi-x1",
   "clock_mhz": 12,
   "notes": "Needs --config-mode spi-x1; the default four-bit mode is wired differently here and configuration fails."
  },
  {
   "id": "openbench-t4",
   "name": "openbench-t4",
   "device": "T4-25K",
   "status": "full",
   "verified": "0.7.2",
   "config_mode": "spi-x4",
   "clock_mhz": 50,
   "notes": "Community design with published schematics, so its pin map in boards/ is trustworthy."
  },
  {
   "id": "marl-45",
   "name": "Marl-45",
   "device": "T4-45K",
   "status": "partial",
   "verified": "0.7.0",
   "config_mode": "spi-x4",
   "clock_mhz": 25,
   "notes": "Builds and runs, but block RAM cascades are unsupported, so no single memory above 4 kbit. A half-full part routes in minutes."
  },
  {
   "id": "crofter-lite",
   "name": "Crofter Lite",
   "device": "M1-8K",
   "status": "partial",
   "verified": "0.7.1",
   "config_mode": "spi-x1",
   "clock_mhz": 25,
   "notes": "No PLL on the part and DDR input registers are unimplemented, so anything above the 25 MHz oscillator is out of reach."
  },
  {
   "id": "thistle-edge",
   "name": "Thistle Edge",
   "device": "T4-12K",
   "status": "partial",
   "verified": "0.6.0",
   "config_mode": "spi-x4",
   "clock_mhz": 12,
   "notes": "Only the internal oscillator is mapped; the external clock pin sits on a bank the device file describes incorrectly. Known bug."
  },
  {
   "id": "dunlin-m1",
   "name": "Dunlin M1",
   "device": "M1-8K",
   "status": "none",
   "verified": null,
   "config_mode": null,
   "clock_mhz": 25,
   "notes": "Bitstreams build correctly but will not load: the board's configuration bridge uses an undocumented protocol nobody has reverse-engineered."
  },
  {
   "id": "harrow-x",
   "name": "Harrow X",
   "device": "GX-2",
   "status": "none",
   "verified": null,
   "config_mode": null,
   "clock_mhz": null,
   "notes": "A third device family entirely. No device file exists and writing one is a months-long measurement job, so it is not planned."
  }
 ]
}