hxta 0.7.2   design uart_loopback   device T4-25K
corner slow: 85 C, 1.14 V, delay table t4.hxd rev 11 (2026-02-18)
clock uncertainty 0.250 ns applied to every capture

clock groups
  name      target        period     achieved    slack        status
  clk_12m   12.00 MHz     83.333 ns  71.4 MHz    +69.333 ns   PASS
  clk_tx    48.00 MHz     20.833 ns  52.1 MHz    +1.646 ns    PASS
  2 clocks, 1 asynchronous crossing NOT analysed (W204: clk_12m -> clk_tx)

worst path, clock clk_tx, slack +1.646 ns
  start   tx_div.count[4]           FF/Q       0.000 ns    0.000
  cell    lut4 u_2871               A -> Y     0.412 ns    0.412
  route   net n_4412 (3 hops)                  1.087 ns    1.499
  cell    lut4 u_2903               B -> Y     0.398 ns    1.897
  route   net n_4461 (2 hops)                  0.731 ns    2.628
  cell    lut4 u_2944               C -> Y     0.406 ns    3.034
  route   net n_4503 (4 hops)                  1.142 ns    4.176
  end     uart_tx.shift[0]          FF/D                   4.176
  setup   requirement                                     20.833
  uncertainty                                             -0.250
  required                                                20.583
  arrival                                                 18.937
  slack = required - arrival                              +1.646  PASS

ten longest paths printed; use --paths to change
derate applied: 0 %   (advice: sign off with --derate 15 on long routes)