[
{
"t": "command",
"k": "hxc",
"s": "Parse the subset, elaborate parameters and generate blocks, flatten hierarchy, emit a gate and register netlist.",
"u": "/reference.html#hxc"
},
{
"t": "flag",
"k": "hxc -o <file>",
"s": "Output netlist path. Default is the input name with .hxn.",
"u": "/reference.html#hxc"
},
{
"t": "flag",
"k": "hxc -I <dir>",
"s": "Add a directory to the `include search path. Repeatable.",
"u": "/reference.html#hxc"
},
{
"t": "flag",
"k": "hxc -D <name>[=<val>]",
"s": "Define a preprocessor macro, as `define would.",
"u": "/reference.html#hxc"
},
{
"t": "flag",
"k": "hxc --top <module>",
"s": "Name the top module explicitly when the file holds several.",
"u": "/reference.html#hxc"
},
{
"t": "flag",
"k": "hxc --param <NAME=VAL>",
"s": "Override a top-level parameter at elaboration. Repeatable.",
"u": "/reference.html#hxc"
},
{
"t": "flag",
"k": "hxc --dump-netlist",
"s": "Also write a human-readable listing next to the .hxn.",
"u": "/reference.html#hxc"
},
{
"t": "flag",
"k": "hxc -v",
"s": "Print each elaboration pass and the final cell and register counts.",
"u": "/reference.html#hxc"
},
{
"t": "command",
"k": "hxsyn",
"s": "Map logic to LUT4s and flip-flops, pack them into tiles, place, then route. Single-threaded and deterministic for a given seed.",
"u": "/reference.html#hxsyn"
},
{
"t": "flag",
"k": "hxsyn --device <part>",
"s": "Target device, one of T4-12K, T4-25K, T4-45K, M1-8K. Required.",
"u": "/reference.html#hxsyn"
},
{
"t": "flag",
"k": "hxsyn -o <file>",
"s": "Routed-design output path. Default is the input name with .hxr.",
"u": "/reference.html#hxsyn"
},
{
"t": "flag",
"k": "hxsyn --seed <n>",
"s": "Placement seed. Changes the result but not its legality; default 1.",
"u": "/reference.html#hxsyn"
},
{
"t": "flag",
"k": "hxsyn --effort {low,medium,high}",
"s": "Placement effort. high is the default and rarely worth lowering.",
"u": "/reference.html#hxsyn"
},
{
"t": "flag",
"k": "hxsyn --max-iters <n>",
"s": "Router iteration cap. Default 40 since 0.7.2; runs needing more never converged.",
"u": "/reference.html#hxsyn"
},
{
"t": "flag",
"k": "hxsyn --report <file>",
"s": "Write the packing and routing summary to a file as well as stdout.",
"u": "/reference.html#hxsyn"
},
{
"t": "command",
"k": "hxta",
"s": "Static timing: clock groups, worst slack per clock, and the longest paths with per-cell delays.",
"u": "/reference.html#hxta"
},
{
"t": "flag",
"k": "hxta --device <part>",
"s": "Device whose delay table to use. Required and must match the .hxr.",
"u": "/reference.html#hxta"
},
{
"t": "flag",
"k": "hxta --corner {fast,typical,slow}",
"s": "Process-voltage-temperature corner. Default slow; sign off on slow.",
"u": "/reference.html#hxta"
},
{
"t": "flag",
"k": "hxta --paths <n>",
"s": "How many of the longest paths to print. Default 10.",
"u": "/reference.html#hxta"
},
{
"t": "flag",
"k": "hxta --clock <name>",
"s": "Restrict the report to one clock group.",
"u": "/reference.html#hxta"
},
{
"t": "flag",
"k": "hxta --derate <pct>",
"s": "Add a flat pessimism percentage to every delay before computing slack.",
"u": "/reference.html#hxta"
},
{
"t": "flag",
"k": "hxta --json",
"s": "Emit the report as JSON, including per-path hop counts, since 0.7.1.",
"u": "/reference.html#hxta"
},
{
"t": "command",
"k": "hxpack",
"s": "Serialise the routed design into the device frame format and append the configuration header.",
"u": "/reference.html#hxpack"
},
{
"t": "flag",
"k": "hxpack --board <name>",
"s": "Board whose pin map and configuration mode to use. Required.",
"u": "/reference.html#hxpack"
},
{
"t": "flag",
"k": "hxpack -o <file>",
"s": "Bitstream output path. Default is the input name with .bit.",
"u": "/reference.html#hxpack"
},
{
"t": "flag",
"k": "hxpack --config-mode {spi-x1,spi-x4}",
"s": "Override the board's configuration width, since 0.7.1. Fenwick A2 needs spi-x1.",
"u": "/reference.html#hxpack"
},
{
"t": "flag",
"k": "hxpack --no-crc",
"s": "Omit the trailing CRC word. For boards whose loader rejects it; off by default.",
"u": "/reference.html#hxpack"
},
{
"t": "code",
"k": "E118 defparam",
"s": "Order-dependent and awkward to elaborate. Use parameter overrides in the instantiation.",
"u": "/codes.html"
},
{
"t": "code",
"k": "E121 hierarchical names in expressions",
"s": "The design is flattened early, so a cross-module reference has nothing to resolve against.",
"u": "/codes.html"
},
{
"t": "code",
"k": "E130 specify blocks, path delays",
"s": "Only meaningful for simulation and cell libraries.",
"u": "/codes.html"
},
{
"t": "code",
"k": "E131 user-defined primitives",
"s": "Table-driven primitives are a simulation feature.",
"u": "/codes.html"
},
{
"t": "code",
"k": "E134 wand, wor, trireg, tri0, tri1",
"s": "No resolved-net modelling exists in the netlist format.",
"u": "/codes.html"
},
{
"t": "code",
"k": "E136 gate primitives beyond and/or/not/xor/buf",
"s": "nmos, pullup, rtran and relatives have no mapping on these devices.",
"u": "/codes.html"
},
{
"t": "code",
"k": "E142 real and time variables",
"s": "Floating-point has no hardware here; use fixed-point integers.",
"u": "/codes.html"
},
{
"t": "code",
"k": "E150 delays in assignments (#n)",
"s": "Timing comes from the delay table, not the source; a # delay is dropped only in an initial, see W301.",
"u": "/codes.html"
},
{
"t": "code",
"k": "E156 casex",
"s": "The don't-care matching of casex hides priority bugs in hardware. Use casez, which warns.",
"u": "/codes.html"
},
{
"t": "code",
"k": "E161 four-state literals (1'bx, 1'bz) outside tri-state IO",
"s": "The netlist is two-state; x and z have no storage.",
"u": "/codes.html"
},
{
"t": "code",
"k": "E170 unpacked arrays deeper than one level",
"s": "Multi-dimensional memories are not inferred yet; planned alongside BRAM cascades.",
"u": "/codes.html"
},
{
"t": "code",
"k": "E181 multiple drivers on a net",
"s": "A resolved wire needs tri-state modelling the format does not have.",
"u": "/codes.html"
},
{
"t": "code",
"k": "W204 unconstrained clock-domain crossing",
"s": "The path is reported but excluded from slack; constrain it with set_false_path or set_max_delay.",
"u": "/codes.html"
},
{
"t": "code",
"k": "W214 array not inferred as block RAM",
"s": "Names the array and the reason; usually an asynchronous read or an odd width.",
"u": "/codes.html"
},
{
"t": "code",
"k": "W301 delay in an initial block",
"s": "The # delay is ignored rather than rejected; initial sets a power-on value only.",
"u": "/codes.html"
},
{
"t": "code",
"k": "W302 system task ignored ($display, $finish)",
"s": "System tasks are accepted and dropped so testbench-flavoured code still elaborates.",
"u": "/codes.html"
},
{
"t": "board",
"k": "Pebble-25 (T4-25K)",
"s": "full \u2014 Reference board. All eight examples build and run; every release is tested here before it is tagged.",
"u": "/board.html?id=pebble-25"
},
{
"t": "board",
"k": "Pebble-12 (T4-12K)",
"s": "full \u2014 Same family, smaller part. vga_bars fits at 71% occupancy and routes in 21 s.",
"u": "/board.html?id=pebble-12"
},
{
"t": "board",
"k": "Fenwick A2 (T4-25K)",
"s": "full \u2014 Needs --config-mode spi-x1; the default four-bit mode is wired differently here and configuration fails.",
"u": "/board.html?id=fenwick-a2"
},
{
"t": "board",
"k": "openbench-t4 (T4-25K)",
"s": "full \u2014 Community design with published schematics, so its pin map in boards/ is trustworthy.",
"u": "/board.html?id=openbench-t4"
},
{
"t": "board",
"k": "Marl-45 (T4-45K)",
"s": "partial \u2014 Builds and runs, but block RAM cascades are unsupported, so no single memory above 4 kbit. A half-full part routes in minutes.",
"u": "/board.html?id=marl-45"
},
{
"t": "board",
"k": "Crofter Lite (M1-8K)",
"s": "partial \u2014 No PLL on the part and DDR input registers are unimplemented, so anything above the 25 MHz oscillator is out of reach.",
"u": "/board.html?id=crofter-lite"
},
{
"t": "board",
"k": "Thistle Edge (T4-12K)",
"s": "partial \u2014 Only the internal oscillator is mapped; the external clock pin sits on a bank the device file describes incorrectly. Known bug.",
"u": "/board.html?id=thistle-edge"
},
{
"t": "board",
"k": "Dunlin M1 (M1-8K)",
"s": "none \u2014 Bitstreams build correctly but will not load: the board's configuration bridge uses an undocumented protocol nobody has reverse-engineered.",
"u": "/board.html?id=dunlin-m1"
},
{
"t": "board",
"k": "Harrow X (GX-2)",
"s": "none \u2014 A third device family entirely. No device file exists and writing one is a months-long measurement job, so it is not planned.",
"u": "/board.html?id=harrow-x"
},
{
"t": "example",
"k": "blink",
"s": "The smallest useful design: one parameter, one counter, one output.",
"u": "/example.html?id=blink"
},
{
"t": "example",
"k": "pwm_fan",
"s": "A comparator against a duty register, and what a wide comparator costs in LUT4s.",
"u": "/example.html?id=pwm_fan"
},
{
"t": "example",
"k": "seven_seg",
"s": "A case decoder plus time-multiplexed digit scanning.",
"u": "/example.html?id=seven_seg"
},
{
"t": "example",
"k": "spi_master",
"s": "A shift register and a small state machine with a clean enable.",
"u": "/example.html?id=spi_master"
},
{
"t": "example",
"k": "bram_rom",
"s": "The exact array shape that gets inferred as block RAM, and nothing else.",
"u": "/example.html?id=bram_rom"
},
{
"t": "example",
"k": "uart_loopback",
"s": "Two clocks, a divider, and the warning you get for an unconstrained crossing.",
"u": "/example.html?id=uart_loopback"
},
{
"t": "example",
"k": "vga_bars",
"s": "A hand-instantiated PLL, 640x480 timing, and a design that actually needs its clock met.",
"u": "/example.html?id=vga_bars"
},
{
"t": "example",
"k": "fifo_cdc",
"s": "The largest example; does not fit M1-8K. A dual-clock FIFO with gray-coded pointers.",
"u": "/example.html?id=fifo_cdc"
},
{
"t": "constraint",
"k": "set_io",
"s": "Map a top-level port to a device pin and optionally an IO standard.",
"u": "/reference.html#constraints"
},
{
"t": "constraint",
"k": "create_clock",
"s": "Declare a clock and its period at a port.",
"u": "/reference.html#constraints"
},
{
"t": "constraint",
"k": "set_input_delay",
"s": "External delay before data arrives at an input, relative to a clock.",
"u": "/reference.html#constraints"
},
{
"t": "constraint",
"k": "set_output_delay",
"s": "External delay required after an output, relative to a clock.",
"u": "/reference.html#constraints"
},
{
"t": "constraint",
"k": "set_false_path",
"s": "Exclude a path from timing; the tool's only way to silence a W204 crossing.",
"u": "/reference.html#constraints"
}
]