{
 "version": "0.7.2",
 "device_default": "T4-25K",
 "examples": [
  {
   "id": "blink",
   "lut4": 25,
   "ff": 24,
   "bram": 0,
   "clock": "12 MHz",
   "file": "blink.v",
   "teaches": "The smallest useful design: one parameter, one counter, one output.",
   "needs_pll": false
  },
  {
   "id": "pwm_fan",
   "lut4": 90,
   "ff": 64,
   "bram": 0,
   "clock": "12 MHz",
   "file": "pwm_fan.v",
   "teaches": "A comparator against a duty register, and what a wide comparator costs in LUT4s.",
   "needs_pll": false
  },
  {
   "id": "seven_seg",
   "lut4": 140,
   "ff": 72,
   "bram": 0,
   "clock": "12 MHz",
   "file": "seven_seg.v",
   "teaches": "A case decoder plus time-multiplexed digit scanning.",
   "needs_pll": false
  },
  {
   "id": "spi_master",
   "lut4": 180,
   "ff": 96,
   "bram": 0,
   "clock": "24 MHz",
   "file": "spi_master.v",
   "teaches": "A shift register and a small state machine with a clean enable.",
   "needs_pll": false
  },
  {
   "id": "bram_rom",
   "lut4": 60,
   "ff": 40,
   "bram": 2,
   "clock": "12 MHz",
   "file": "bram_rom.v",
   "teaches": "The exact array shape that gets inferred as block RAM, and nothing else.",
   "needs_pll": false
  },
  {
   "id": "uart_loopback",
   "lut4": 310,
   "ff": 180,
   "bram": 0,
   "clock": "12 / 48 MHz",
   "file": "uart_loopback.v",
   "teaches": "Two clocks, a divider, and the warning you get for an unconstrained crossing.",
   "needs_pll": true
  },
  {
   "id": "vga_bars",
   "lut4": 980,
   "ff": 412,
   "bram": 0,
   "clock": "25.175 MHz",
   "file": "vga_bars.v",
   "teaches": "A hand-instantiated PLL, 640x480 timing, and a design that actually needs its clock met.",
   "needs_pll": true
  },
  {
   "id": "fifo_cdc",
   "lut4": 2140,
   "ff": 1180,
   "bram": 4,
   "clock": "12 / 48 MHz",
   "file": "fifo_cdc.v",
   "teaches": "The largest example; does not fit M1-8K. A dual-clock FIFO with gray-coded pointers.",
   "needs_pll": true
  }
 ]
}